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?2002 silicon storage technology, inc. s71131-03-000 9/02 344 1 the sst logo, superflash, and flashflex are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. data sheet features: ? 8-bit 8051-compatible microcontroller (mcu) with embedded superflash memory ? fully software compatible ? development toolset compatible ? pin-for-pin package compatible sst89c54/58 operation ? 0 to 33mhz at 5v 256 bytes internal ram dual block superflash eeprom ? sst89c58: 32 kbyte primary block (128-byte sector size) + 4 kbyte secondary block (64-byte sector size) ? sst89c54: 16 kbyte primary block (128-byte sector size) + 4 kbyte secondary block (64-byte sector size) ? individual block security lock with softlock ? concurrent operation during in-application programming (iap) ? memory re-mapping for interrupt support during iap support external address range up to 64 kbyte of program and data memory three high current drive ports (16 ma each) three 16-bit timers/counters full-duplex serial port (uart) six interrupt sources at 2 priority levels programmable watchdog timer (wdt) four 8-bit i/o ports (32 i/o pins) ttl- and cmos-compatible logic levels low power modes ? power-down mode with external interrupt wake-up ? standby (stop clock) low voltage at 2.7v (0 to 12mhz) pdip-40, plcc-44 and tqfp-44 packages temperature ranges: ? commercial (0c to +70c) ? industrial (-40c to +85c) product description the sst89c54 and sst89c58 are members of the flashflex51 family of 8-bit microcontroller products designed and manufactured with the state-of-the-art superflash cmos semiconductor process technology. the device uses the same 8051 instruction set and is pin- for-pin compatible with standard 8051 microcontroller devices. the device comes with 20/36 kbyte of on-chip flash eeprom program memory using sst?s patented and pro- prietary cmos superflash eeprom technology with sst?s field-enhancing, tunneling injector, split-gate memory cells. the superflash memory is partitioned into 2 indepen- dent program memory blocks. the primary superflash block 0 occupies 16/32 kbyte of internal program memory space and the secondary superflash block 1 occupies 4 kbyte of internal program memory space. the 4 kbyte secondary superflash block can be mapped to the highest or lowest location of the 64 kbyte address space; it can also be hidden from the program counter and used as an inde- pendent eeprom-like data memory. the flash memory blocks can be programmed via a standard 87c5x otp eprom programmer fitted with a special adapter and firm- ware for sst?s devices. during the power-on reset, the device can be configured as a slave to an external host for source code storage or as a master to an external host for an in-application programming (iap) operation. the device is designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility. the device is pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user pro- gram code loading or subsequent user code updating via the iap operation. an example of bootstrap loader is avail- able for the user?s reference and convenience only. sst does not guarantee the functionality nor the usefulness of the sample bootstrap loader. chip-erase operations will erase the pre-programmed sample code. in addition to 20/36 kbyte of superflash eeprom pro- gram memory on-chip, the device can address up to 64 kbyte of external program memory. in addition to 256 x8 bits of on-chip ram, up to 64 kbyte of external ram can be addressed. sst?s highly reliable, patented superflash technology and memory cell architecture have a number of impor- tant advantages for designing and manufacturing flash eeproms. these advantages translate into signifi- cant cost and reliability benefits for our customers. flashflex51 mcu sst89c54 / sst89c58 sst89C5Xflashflex51 mcu
2 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 table of contents product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 program flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 memory re-mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 data ram memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 external host programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 in-application programming mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.0 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.0 serial i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.0 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.0 security lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 hard lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 softlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 security lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.0 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
data sheet flashflex51 mcu sst89c54 / sst89c58 3 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 10.0 power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.1 power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 standby mode (stop clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.0 clock input options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.1 recommended capacitor values for crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12.0 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 absolute maximum stress ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.2 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3 flash memory programming timing diagrams with external host mode . . . . . . . . . . . . . . . . . . . . . . 46 13.0 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.0 packaging diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 list of figures figure 2-1: pin assignments for 40-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2-2: pin assignments for 44-lead tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2-3: pin assignments for 44-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3-1: sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3-2: sst89c54 program memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3-3: sst89c58 program memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3-4: sst89c54 re-mapped program memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3-5: sst89c58 re-mapped program memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4-1: i/o pin assignments for external host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 figure 7-1: block diagram of programmable watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 8-1: security lock levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10-1: power-on reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 11-1: oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12-1: external program memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 figure 12-2: external data memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12-3: external data memory write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12-4: external clock drive waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12-5: shift register mode timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 12-6: ac input/output test waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 12-7: float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 12-8: a test load example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12-9: i dd test condition, active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12-10: i dd test condition, power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12-11: i dd test condition, standby (stop clock) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12-12: read-id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 12-13: chip-erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 12-14: block-erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 12-15: sector-erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 12-16: byte-program; prog-sb3, prog-sb2, prog-sb1, prog-rb1, and prog-rb0 . . . . . . . . . . . 48 figure 12-17: burst-program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 12-18: byte-verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
data sheet flashflex51 mcu sst89c54 / sst89c58 5 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 list of tables table 2-1: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3-1: re-mapping table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3-2: flashflex51 sfr memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3-3: cpu related sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3-4: flash memory programming sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3-5: watchdog timer sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3-6: timer/counters sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3-7: interface sfrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4-1: external host mode commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4-2: product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4-3: in-application programming mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8-1: security lock options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8-2: security lock access table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10-1: sst89c54/58 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11-1: recommended values for c1 and c2 by crystal type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 12-1: operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12-2: reliability characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12-3: ac conditions of test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12-4: recommended system power-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12-5: pin impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12-6: dc electrical characteristics for 33mhz devices; 4.5-5.5v . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 12-7: dc electrical characteristics for 12mhz devices; 3.0-3.6v . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12-8: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 12-9: external clock drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 12-10: serial port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 12-11: flash memory programming/verification parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 1.0 functional blocks 6 interrupts superflash eeprom primary block 16k/32k x8 1 secondary block 4k x8 i/o i/o i/o i/o oscillator interrupt control 8051 cpu core ram 256 x8 security lock watchdog timer fcu i/o port 0 i/o port 1 i/o port 2 i/o port 3 8-bit uart timer 0 (16-bit) timer 1 (16-bit) timer 2 (16-bit) 8 8 8 8 8 344 ill b1.2 1. 16k x 8 for sst89c54 32k x 8 for sst89c58 fcu = flash control unit 8051 cpu core = alu, acc, b-reg., instruction reg., pc, timing and control, etc. f unctional b lock d iagram
data sheet flashflex51 mcu sst89c54 / sst89c58 7 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 2.0 pin assignments figure 2-1: p in a ssignments for 40- pin pdip figure 2-2: p in a ssignments for 44- lead tqfp figure 2-3: p in a ssignments for 44- lead plcc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 (t2) p1.0 (t2ex) p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rst (rxd) p3.0 (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) 40-pin pdip top view 344 40-pdip pi p1.3 (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 344 44-tqfp tqj p2.4 44-lead tqfp top view p1.4 p1.3 p1.2 p1.1 (t2ex) p1.0 (t2) nc vdd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p1.5 p1.6 p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# nc ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) nc = no connect (reserved) 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 p1.5 p1.6 p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0#) p3.2 (int1#) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea# nc ale/prog# psen# p2.7 (a15) p2.6 (a14) p2.5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 p1.4 p1.3 p1.2 p1.1 (t2ex) p1.0 (t2) nc v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr#) p3.6 (rd#) p3.7 xtal2 xtal1 v ss nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 44-lead plcc top view 344 44-plcc nj p3.3 nc = no connect (reserved)
8 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 2.1 pin descriptions table 2-1: p in d escriptions (1 of 2) symbol type 1 name and functions p0[7:0] i/o port 0: port 0 is an 8-bit open drain bi-directional i/o port. as an output port each pin can sink several ls ttl inputs. port 0 pins that have ?1?s written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. in this application it uses strong internal pull-ups when transitioning to ?1?s. port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during external host mode ver- ification. external pull-ups are required during program verification or as a general purpose i/ o port. p1[7:0] i/o with internal pull-ups port 1: port 1 is an 8-bit bi-directional i/o port with internal pull-ups. port 1 output buffers can drive ls ttl inputs. port 1 pins that have ?1?s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current (i il , see tables 12-6 and 12-7) because of the internal pull-ups. p1[5, 6, 7] have high current drive of 16ma. port 1 also receives the low-order address bytes during external host mode programming and verification. p1[0] i t2: external count input to timer/counter 2 p1[1] i t2ex: timer/counter 2 capture/reload trigger p2[7:0] i/o with internal pull-ups port 2: port 2 is an 8-bit bi-directional i/o port with internal pull-ups. port 2 pins that have ?1?s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current (i il , see tables 12-6 and 12-7) because of the internal pull-ups. port 2 sends the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit address (movx@dptr). in this application it uses strong internal pull-ups when outputting ?1?s. port 2 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification. p3[7:0] i/o with internal pull-ups port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. the port 3 output buffers can drive ls ttl inputs. port 3 pins that have ?1?s written to them are pulled high by the inter- nal pull-ups, and in that state can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current (i il , see tables 12-6 and 12-7) because of the internal pull-ups. port 3 serves the functions of various special features of the device. port 3 also receives some control signals and a partial of high-order address bits during the external host mode programming and verification. p3[0] i rxd: uart - receive input p3[1] o txd: uart - transmit output p3[2] i int0#: external interrupt 0 input p3[3] i int1#: external interrupt 1 input p3[4] i t0: external count input to timer/counter 0 p3[5] i t1: external count input to timer/counter 1 p3[6] o wr#: external data memory write strobe p3[7] o rd#: external data memory read strobe psen# i/o program store enable: psen# is the read strobe to external program memory. when the device is executing code from internal program memory, psen# is inactive (?h?). when the device is executing code from external program memory, psen# is activated twice each machine cycle, except that two psen# activations are skipped during each access to exter- nal data memory. while the rst input is continually held high (for more than ten machine cycles), a forced high-to-low input transition on the psen# pin will bring the device into the external host mode programming.
data sheet flashflex51 mcu sst89c54 / sst89c58 9 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 rst i reset: a high logic state on this pin for two machine cycles, while the oscillator is running, will reset the device. if the psen# pin is driven by a high-to-low input transition while the rst input pin is held high, the device will enter the external host mode. otherwise, the device will enter the normal operation mode. ea# i external access enable: ea# 2 must be connected to v il in order to enable the device to fetch code from external program memory. ea# must be strapped to v ih for internal program execution. however, security lock level 4 will disable ea#, and program execution is only pos- sible from internal program memory. the ea# pin can tolerate a high voltage 3 of 12v (see electrical specification, section 12.0). ale/ prog# 4 i/o address latch enable: ale is the output signal for latching the low byte of the address dur- ing an access to external memory. this pin is also the programming pulse input (prog#) for flash programming. normally the ale 5 is emitted at a constant rate of 1/6 the crystal fre- quency and can be used for external timing and clocking. one ale pulse is skipped during each access to external data memory. xtal1 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generation circuits. xtal2 o crystal 2: output from the inverting oscillator amplifier. v dd i power supply v ss i ground t2-1.9 344 1. i = input; o = output 2. ea# is not sampled and latched on reset after level 2 or level 3 locked. mcu will jump to run internal code if ea# changes fr om v il to v ih . this is a security compromise. use level 4 lock to fix. 3. it is not necessary to receive a 12v programming supply voltage during flash programming. 4. applying 10-50 k ? pull-up resistor to this pin may improve the device?s performance. 5. ale loading issue: when ale pin experiences higher loading (>30pf ) during the reset, the mcu may accidentally enter into mode s other than normal working mode. the solution is to add a pull-up resistor of 3-50 k ? to v dd , e.g. for ale pin. table 2-1: p in d escriptions (2 of 2) symbol type 1 name and functions
10 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 3.0 memory organization the sst89c54/58 has separate address spaces for pro- gram and data memory. 3.1 program flash memory there are two internal flash memory blocks in the sst89c54/58. the primary flash memory block 0 has 16/32 kbyte and occupies the address space 0000h to 3fffh/7fffh. the secondary flash memory block 1 has 4 kbyte and occupies the address space f000h to ffffh. the 16/32k x8 primary superflash block is organized into 128/256 sectors. each sector contains 2 rows and each row has 64 bytes. the 4k x8 secondary superflash block is organized into 64 sectors. each sector contains 2 rows. each row con- tains 32 bytes. figure 3-1 shows the sector organization for sst89c54/58. when internal code operation is enabled (ea# = 1), the pri- mary 16/32 kbyte flash memory block is always visible to the program counter for code fetching. figures 3-2 and 3-3 show the program memory organizations for the sst89c54/58. when internal code operation is enabled (ea# = 1), the secondary 4 kbyte flash memory block is selectively visi- ble for code fetching. when bit 7 of the superflash con- figuration mailbox register (sfcf[7]), is set, the secondary 4 kbyte block will be visible for code fetching. 3.1.1 code corruption due to brown-out the mcu will still run a user?s application code even if the v dd drops down to 2v, far below the minimum working volt- age of 2.7v. this can cause the program counter (pc) to get lost and sometimes lead to code corruption. the solu- tion is to use an off-chip voltage supervisory chip to keep the mcu in reset state whenever the v dd drops below 2.7v. figure 3-1: s ector o rganization 7fffh 7f80h 4000h 3fffh 0000h block 0 (16/32 kbyte) 344 ill f47.7 sector 255 sector 127 sector 0 3f80h 007fh ffffh ffc0h f03fh block 1 (4 kbyte) primary secondary sector 63 sector 0 f000h 89c58 89c54
data sheet flashflex51 mcu sst89c54 / sst89c58 11 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 3-2: sst89c54 p rogram m emory o rganization figure 3-3: sst89c58 p rogram m emory o rganization 344 ill f21.2 48 kbyte external 64 kbyte external 16 kbyte internal (block 0) 44 kbyte external 16 kbyte internal (block 0) 4 kbyte internal (block 1) ea# = 1 & sfcf[7] = 1 ea# = 1 & sfcf[7] = 0 ea# = 0 ffffh efffh f000h 4000h 0000h 3fffh ffffh 4000h 0000h ffffh 0000h 3fffh 344 ill f11.2 32 kbyte external 64 kbyte external 32 kbyte internal (block 0) 28 kbyte external 32 kbyte internal (block 0) 4 kbyte internal (block 1) ea# = 1 & sfcf[7] = 1 ea# = 1 & sfcf[7] = 0 ea# = 0 ffffh efffh f000h 8000h 0000h 7fffh ffffh 8000h 0000h ffffh 0000h 7fffh
12 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 3.2 memory re-mapping the sst89c54/58 memory re-mapping feature allows users to re-map the secondary flash memory block physi- cal address to overlay the lower order logical address so that interrupts can be serviced when the primary flash memory block (block 0) is busy under program/erase operation. since block 0 occupies the low order program address space of the 8051 architecture where the interrupt vectors reside, those interrupt vectors will normally not be available when block 0 is being programmed. sst89c54/58 provides four options of memory re-map- ping (refer to table 3-1). when the lowest 4 kbyte are re- mapped, any program access within logical address range 0000h-0fffh will have the 4 most significant address bits forced to ?1?, redirecting the access to f000h-ffffh. note that the physical contents of the overlaid portion of block 0 (i.e. physical locations 0000h-0fffh in the current exam- ple) will not be addressable by the program counter, but only accessible through iap registers. block 1 is still acces- sible through f000h-ffffh. block 1 is addressable by the program counter in both logical address ranges 0000h- 0fffh and f000h-ffffh. 3.2.1 activation and deactivation of memory re-mapping the actual amount of memory that is re-mapped is con- trolled by map-en[1:0] bits as shown in table 3-1. the map- en[1:0] bits are the same bits as sfcf[1:0]. the map- en[1:0] bits are under software control and can be changed during program execution. si nce changing re-mapping will cause program re-location, it is advisable that the instruction that changes the map-en[1:0] be in the portion of memory that is not affected by the re-mapping change. (see figures 3-4 and 3-5 and the application note, memory re-mapping of the sst89c54/58 microcontroller ). the map-en[1:0] bits are initialized at reset according to the contents of two non-volatile register bits, re-map[1:0]. the re-map[1:0] bits are programmed via prog_rb1 and prog_rb0 external host mode and iap commands. refer to ?external host programming mode? in section 4.1 or iap section for description. the contents of map-en[1:0] are only updated according to re-map[1:0] on a successful reset. any subsequent alter- ation to the re-map[1:0] bits will not automatically change the map-en[1:0] bits without a reset. similarly, changes to map-en[1:0] during program execution will not change re- map[1:0] bits. to deactivate memory re-mapping, a chip-erase operation will revert re-map[1:0] to the default status of ?11?, dis- abling re-map. programming 00b to map-en register also deactivates memory re-mapping, during the run time. table 3-1: r e - mapping t able re-map[1:0] 1 1. map-en[1:0] are nonvolatile registers which are examined only during reset. map-en 2,3 2. map-en[1:0] are initialized according to re-map[1:0] during reset. 3. map-en[1:0] are located in sfcf[1:0], they determine the re-mapping configuration. they may be changed by the program at run time. comments 11 00 re-mapping is turned off. program memory is in normal configuration. 10 01 1 kbyte of flash memory location is re-mapped. program access to location 0000h-03ffh is redirected to f000h-f3ffh. 01 10 2 kbyte of flash memory location are re-mapped. program access to location 0000h-07ffh is redirected to f000h-f7ffh. 00 11 4 kbyte of flash memory location is re-mapped. program access to location 0000h-0fffh is redirected to f000h-ffffh. t3-1.4 344
data sheet flashflex51 mcu sst89c54 / sst89c58 13 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 3-4: sst89c54 r e - mapped p rogram m emory o rganization figure 3-5: sst89c58 r e - mapped p rogram m emory o rganization 44 kbyte external 15/14/12 kbyte internal (block 0) 1/2/4 kbyte internal (block 1) 4 kbyte internal (block 1) ea# = 1 & sfcf[7] = x sfcf [1:0] = 01/10/11 ffffh efffh f000h 3fffh 4000h 0000h 344 ill f35.5 28 kbyte external 31/30/28 kbyte internal (block 0) 1/2/4 kbyte internal (block 1) 4 kbyte internal (block 1) ea# = 1 & sfcf[1] = x sfcf [1:0] = 01/10/11 ffffh efffh f000h 7fffh 8000h 0000h 344 ill f36.3
14 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 3.3 data ram memory sst89c54/58 have 256 bytes x8 bits internal ram and can address up to 64 kbyte of external data memory. 3.4 special function registers most of the unique features of the flashflex51 microcontroller family are controlled by bits in special function regis- ters (sfrs) located in the flashflex51 sfr memory map shown below. individual descriptions of each sfr are provided and reset values indicated in tables 3-3 to 3-7. 3.4.1 sst89c54/58 special function registers table 3-2: f lash f lex 51 sfr m emory m ap 8 bytes f8h ffh f0h b 1 1. sfrs are bit addressable. f7h e8h efh e0h acc 1 e7h d8h dfh d0h psw 1 d7h c8h t2con 1 rcap2l rcap2h tl2 th2 cfh c0h wdtc 1 c7h b8h ip 1 bfh b0h p3 1 sfcf sfcm sfal sfah sfdt sfst b7h a8h ie 1 afh a0h p2 1 a7h 98h scon 1 sbuf 9fh 90h p1 1 97h 88h tcon 1 tmod tl0 tl1 th0 th1 8fh 80h p0 1 sp dpl dph wdtd pcon 87h t3-2.1 344 table 3-3: cpu related sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb acc 1 1. bit addressable sfrs accumulator e0h acc[7:0] 00h b* b register f0h b[7:0] 00h psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h sp stack pointer 81h sp[7:0] 07h dpl data pointer low 82h dpl[7:0] 00h dph data pointer high 83h dph[7:0] 00h ie* interrupt enable a8h ea - et2 es et1 ex1 et0 ex0 00h ip* interrupt priority b8h - - pt2 ps pt1 px1 pt0 px0 xx000000b pcon power control 87h smod - - - gf1 gf0 pd - 0xxx0000b t3-3.6 344
data sheet flashflex51 mcu sst89c54 / sst89c58 15 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 symbol function vis upper flash block visibility. 1: 4 kbyte flash block visible from f000h-ffffh. 0: 4 kbyte flash block not visible. the vis bit is ignored when re-map is in effect: the vis bit is ?don?t care? after re-mapped 1kb, 2kb or 4kb. vis controls the visibility of block 1 to program counter (pc) only when re-map is 0 kbyte. iapen enable iap operation. 1: iap commands are enabled. 0: iap commands are disabled. map-en1 map enable bit 1. map-en0 map enable bit 0. map-en[1:0] are initialized to default value according to re-map[1:0] during reset. refer to table 3-1. table 3-4: f lash m emory p rogramming sfr s symbol description direct address bit address, symbol, or alternative port function reset value msb lsb sfcf superflash configuration b1h vis iapen - - - - map-en 00xxxxxxb sfcm superflash command b2h fie fcm 00h sfal superflash address low b3h superflash low order byte address register - a7 to a0 (sfal) 00h sfah superflash address high b4h superflash high order byte address register - a15 to a8 (sfah) 00h sfdt superflash data b5h superflash data register 00h sfst superflash status b6h sb[2:0] - busy flash_busy - - xxxx00xxb t3-4.7 344 superflash configuration register (sfcf) location76543210reset value b1h vis iapen ---- map-en1 map-en0 00xxxxxxb
16 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 symbol function fie flash interrupt enable. 1: int1# is re-assigned to signal iap operation completion. external int1# interrupts are ignored. 0: int1# is not reassigned. fcm[6:0] flash operation command. 000_0001b chip-erase 000_0110b burst-program 000_1011b sector-erase 000_1100b byte-verify 1 000_1101b block-erase 000_1110b byte-program 000_1111b prog-sb1 2 000_0011b prog-sb2 2 000_0101b prog-sb3 2 000_1000b prog-rb0 2 000_1001b prog-rb1 2 all other combinations are not implemented, and reserved for future use. 1. byte-verify has a single machine cycle latency and wil l not generate any int1# interrupt regardless of fie. 2. these commands must reside in block 0 (32 kbyte block) only or external code memory. symbol function sfal mailbox register for interfacing with flash memory block. (low order address register). symbol function sfah mailbox register for interfacing with flash memory block. (high order address register). symbol function sfdt mailbox register for interfacing with flash memory block. (data register). superflash command register (sfcm) location76543210reset value b2h fie fcm6 fcm5 fcm4 fc m3 fcm2 fcm1 fcm0 00000000b superflash address register (sfal) location76543210reset value b3h superflash low order byte address register 00000000b superflash address register (sfah) location76543210reset value b4h superflash high order byte address register 00000000b superflash data register (sfdt) location76543210reset value b5h superflash data register 00000000b
data sheet flashflex51 mcu sst89c54 / sst89c58 17 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 symbol function sb1 security bit 1. sb2 security bit 2. sb3 security bit 3. please refer to table 8-1 for security lock options. busy burst-program completion polling bit. 1: device is busy with flash operation. 0: device is available for next burst-program operation. flash_busy flash operation completion polling bit. 1: device is busy with flash operation. 0: device has fully completed the last command, including burst-program. symbol function wdre watchdog timer reset enable. 1: enable watchdog timer reset. 0: disable watchdog timer reset. wdts watchdog timer reset flag. 1: hardware sets the flag on watchdog overflow. 0: external hardware reset clears the flag. flag can also be cleared by writing a 1. flag survives if chip reset happened because of watchdog timer overflow. wdt watchdog timer refresh. 1: software sets the bit to force a watchdog timer refresh. 0: hardware resets the bit when refresh is done. swdt start watchdog timer. 1: start wdt. 0: stop wdt. symbol function wdtd initial/reload value in watchdog timer, new value won?t be effective until wdt is set. superflash status register (sfst) (read only register) location76543210reset value b6h sb1 sb2 sb3 - busy flash_busy - - xxxx00xxb table 3-5: w atchdog t imer sfr s wdtc 1 1. bit addressable sfrs watchdog timer control c0h - - - - wdre wdts wdt swdt x0h wdtd watchdog timer data/reload 86h 00h t3-5.3 344 watchdog timer control register (wdtc) location76543210reset value c0h---- wdre wdts wdt swdt xxxx0000b watchdog timer data/reload register (wdtd) location76543210reset value 86h watchdog timer data/reload 00000000b
18 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 table 3-6: t imer /c ounters sfr s tmod timer/counter mode control 89h timer 1 timer 0 00h gate c/t# m1 m0 gate c/t# m1 m0 tcon 1 timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th0 timer 0 msb 8ch th0[7:0] 00h tl0 timer 0 lsb 8ah tl0[7:0] 00h th1 timer 1 msb 8dh th1[7:0] 00h tl1 timer 1 lsb 8bh tl1[7:0] 00h t2con 1 timer / counter 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# 00h th2 timer 2 msb cdh th2[7:0] 00h tl2 timer 2 lsb cch tl2[7:0] 00h rcap2h timer 2 capture msb cbh rcap2h[7:0] 00h rcap2l timer 2 capture lsb cah rcap2l[7:0] 00h t3-6.1 344 1. bit addressable sfrs note: t2mod register is not implemented. table 3-7: i nterface sfr s sbuf serial data buffer 99h sbuf[7:0] indeterminate scon 1 1. bit addressable sfrs serial port control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h p0 1 port 0 80h p0[7:0] ffh p1 1 port 1 90h - - - - - - t2 ex t2 ffh p2 1 port 2 a0h p2[7:0] ffh p3 1 port 3 b0h rd# wr# t1 t0 int1# int0# txd rxd ffh t3-7.5 344
data sheet flashflex51 mcu sst89c54 / sst89c58 19 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 4.0 flash memory programming the sst89c54/58 internal flash memory can be pro- grammed or erased using the following two methods: external host mode in-application programming (iap) mode 4.1 external host programming mode external host programming mode allows the user to pro- gram the flash memory directly without using the cpu. external host mode is entered by forcing psen# from a logic high to a logic low while rst input is being held con- tinuously high. the device will stay in external host mode as long as rst = ?1? and psen# = ?0?. a read-id operation is necessary to ?arm? the device, no other external host mode command can be enabled until a read-id is performed. in external host mode, the internal flash memory blocks are accessed through the re- assigned i/o port pins (see figure 4-1 for details) by an external host, such as an mcu programmer, pcb tester or a pc controlled development board. when the chip is in the external host mode, port 0 pins are assigned to be the parallel data input and output pins. port 1 pins are assigned to be the non-multiplexed low order address bus signals for the internal flash memory (a 7 -a 0 ). the first six bits of port 2 pins (p2[5:0]) are assigned to be the non-multiplexed upper order address bus signals for the internal flash memory (a 13 -a 8 ) along with two of the port 3 pins (p3[5] as a 15 and p3[4] as a 14 ). two upper order port 2 pins (p2[7] and p2[6]) and two upper order port 3 pins (p3[7] and p3[6]) along with rst, psen#, ale/ prog#, ea# pins are assigned as the control signal pins. the port 3 pin (p3[3]) is assigned to be the ready/busy sta- tus signal, which can be used for handshaking with the external host during a flash memory programming opera- tion. the flash memory programming operation (erase, program, verify, etc.) is internally self-timed. the insertion of an ?arming? command prior to entering the external host mode by utilizing the read-id operation pro- vides additional protection for inadvertent writes to the internal flash memory caused by a noisy or unstable sys- tem environment during power-up or brown-out conditions. the external host mode uses twelve (12) hardware com- mands, which are decoded from the control signal pins, to facilitate the internal flash memory erase, program and ver- ify processes. the external host mode is enabled on the falling edge of psen#. the external host mode commands are enabled on the falling edge of ale/prog#. the list in table 4-1 outlines all the commands and the respective control signal assignment. table 4-1: e xternal h ost m ode c ommands operation rst psen# ale/ prog# ea# p3[7] p3[6] p2[7] p2[6] p0[7:0] p1[7:0] p3[5:4] p2[5:0] read-id v ih1 v il v ih v ih v il v il v il v il do al ah chip-erase v ih1 v il ? 1 1. symbol ? signifies a negative pulse and the command is asserted during the low state of ale/prog# input. all other combinations of the above input pins are invalid and may result in unexpected behaviors. note: v il = input low voltage; v ih = input high voltage; v ih1 = locig high level (rst); x = don?t care; al = address low order byte; ah = address high order byte; di = data input; do = data output; a[15:12] = 0xxxb for block 0 (sst89c58), a[15:12] = 00xxb for block 0 (sst89c54), and a[15:12] = ?1111b? for block 1. v ih v il v il v il v ih xx x block-erase v ih1 v il ? v ih v ih v ih v il v ih xxa[15:12] sector-erase v ih1 v il ? v ih v ih v il v ih v ih xalah byte-program v ih1 v il ? v ih v ih v ih v ih v il di al ah burst-program v ih1 v il ? v ih v il v ih v ih v il di al ah byte-verify (read) v ih1 v il v ih v ih v ih v ih v il v il do al ah prog-sb1 v ih1 v il ? v ih v ih v ih v ih v ih xx x prog-sb2 v ih1 v il ? v ih v il v il v ih v ih xx x prog-sb3 v ih1 v il ? v ih v il v ih v il v ih xx x prog-rb0 v ih1 v il ? v ih v ih v il v il v il xx x prog-rb1 v ih1 v il ? v ih v ih v il v il v ih xx x t4-1.5 344
20 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 4-1: i/o p in a ssignments for e xternal h ost m ode 4.1.1 product identification the read-id command accesses the signature bytes that identify the device as an sst89c54/58 and the manufac- turer as sst (see table 4-2). external programmers pri- marily use these signature bytes in the selection of programming algorithms. the read-id command is selected by the byte code of 00h on p2[7:6] and p3[7:6]. see figure 12-12 for timing waveforms. 4.1.2 arming command an arming command sequence must take place before any external host mode sequence command is recognized by the sst89c54/58. this prevents accidental triggering of external host mode commands due to noise or program- mer error. the arming command is as follows: 1. psen# goes low while rst is high. this will set the device in external host mode, re-configuring the pins. 2. a read-id command is issued and held for 1 ms. after the above sequence, all other external host mode commands are enabled. before the read-id command is received, all other external host commands received are ignored. flash control signals address bus a7-a0 flash control signals address bus a13-a8 input/ output data bus port 0 v ss xtal1 xtal2 busy/ready port 3 v dd rst port 2 port 1 ea# ale / prog# psen# 7 6 5 a15 a14 4 3 2 1 0 7 6 7 6 5 4 3 2 1 0 0 7 6 0 address bus a15-a14 344 ill f01.2 table 4-2: p roduct i dentification address data manufacturer?s id 30h bfh device id sst89c54 31h e4h sst89c58 31h e2h t4-2.2 344
data sheet flashflex51 mcu sst89c54 / sst89c58 21 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 4.1.3 external host mode commands the twelve sst89c54/58 external host mode commands are read-id, chip-erase, block-erase sector-erase, byte- program, burst-program, byte-verify, prog-sb1, prog- sb2, prog-sb3, prog-rb0 and prog-rb1. see table 4-1 for all signal logic assignments and table 12-11 for the tim- ing parameter for the external host mode commands. the critical timing for all erase and program commands is self- generated by the on-chip flash memory controller. the high-to-low transition of the prog# signal initiates the erase and program commands, which are synchronized internally. the read commands are asynchronous reads, independent of the prog# signal level. the following three commands are used for erasing all or part of the memory array. memory locations that are to be programmed must be in the erased state (0ffh) prior to programming. the chip-erase command erases all bytes in both memory blocks. this command ignores the security lock status and will erase the security bits and the re-map bits. see figure 12-13 for timing waveforms. the block-erase command erases all bytes in one of the memory blocks (16/32kb or 4kb). this command will not be enabled if the security lock is enabled on the selected memory block. the selection of the memory block to be erased is determined by a[15:12]. if a15 is a ?0?, then the primary flash memory block 0 (16/32kb), is selected. if a[15:12] = ?1111b?, then the secondary flash memory block 1 (4kb) is selected. see figure 12-14 for the timing waveforms. the sector-erase command erases all of the bytes in a sector. the sector size for the primary flash memory (addresses 0000h-3fffh/7fffh) is 128 bytes. the sec- tor size for the secondary flash memory (addresses f000h-ffffh) is 64 bytes. this command will not be exe- cuted if the security lock is enabled on the selected mem- ory block. the selection of the memory sector to be erased is determined by a[15:6] for block 0 a[15:5] for block 1. see figure 12-15 for timing waveforms. the byte-program and burst-program commands are used for programming new data into the memory array. selection of which program command to use will be dependent upon the desired programming field size. pro- gramming will not take place if any security locks are enabled on the selected memory block. the byte-program command programs data into a single byte. see figure 12-16 for timing waveforms. the burst-program command programs data to an entire row, sequentially byte-by-byte. see figure 12-17 for timing waveforms. the byte-verify command allows the user to verify that the sst89c54/58 correctly performed an erase or program command. this command will be disabled if any security locks are enabled on the selected memory block. see fig- ure 12-18 for timing waveforms. the prog-sb1, prog-sb2, prog-sb3 commands program the security bits. the functions of these bits are described in a security lock section and also in table 8-1. once pro- grammed, these bits can only be erased through a chip- erase command. the prog-rb1, and prog-rb0 commands program the re-map[1:0] bits. the functions of these bits are described in the memory re-mapping section and also in table 3-1. once programmed, these bits can only be erased through chip-erase command.
22 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 4.1.4 external host mode clock source in external host mode, an internal oscillator will provide clocking for the sst89c54/58. the on-chip oscillator will be turned on as the sst89c54/58 enters external host mode; i.e. when psen# goes low while rst is high. the oscillator provides both clocking for the flash control unit as well as timing references for program and erase opera- tions. during external host mode, the cpu core is held in reset. upon exit from external host mode, the internal oscil- lator is turned off. the same oscillator also provides the time base for the watchdog timer and timing references for iap mode pro- gram and erase operations. see more detailed description in later sections. 4.1.5 flash operation status detection via external host handshake the sst89c54/58 provide two methods for an external host to detect the completion of a flash memory operation to optimize the program or erase time. the end of a flash memory operation cycle can be detected by: 1) monitoring the ready/busy# bit at p3[3]; 2) monitoring the data# polling bit at p0[7] and p0[3]. 4.1.5.1 ready/busy# (p3[3]) the progress of the flash memory programming can be monitored by the ready/busy# output signal. p3[3] is driven low, some time after ale/prog# goes low during a flash memory operation to indicate the busy# status of the flash control unit (fcu). p3[3] is driven high when the flash programming operation is completed to indicate the ready status. during a burst-program operation, p3[3] is driven high (ready) in between each byte programmed among the burst to indicate the ready status to receive the next byte. when the external host detects the ready status after a byte among the burst is programmed, it should then put the data/address (within the same row) of the next byte on the bus and drive ale/prog# low (pulse), before the time-out limit expires. see table 12-11 for details. burst-program command presented after time-out will wait until the next cycle. therefore, it will have longer programming time. 4.1.5.2 data# polling (p0[7] and p0[3]) during a program operation, any attempts to read (byte- verify), while the device is busy, will receive the comple- ment of the data for the last byte loaded (logic low, i.e. ?0? for an erase) on p0[3] and p0[7] with the rest of the bits ?0?. during a program operation, the byte-verify command will read the data from the last byte loaded, not the data at the address specified. during a burst-program operation, the true data will be read from p0[7], when the device completes each byte pro- grammed among the burst to indicate the ready status to receive the next byte. when the external host detects the ready status after a byte among the burst is programmed, it should then put the data/address (in the same row) of the next byte on the bus and drive ale/prog# low immedi- ately, before the time-out limit expires (see table 12-11 for details.). the true data will be read from p0[3], when the burst-program command is terminated and the device is ready for the next operation. after security lock-bits are set: if read on universal programmer, e.g. external host mode, the programmer will read 00h instead of 0ffh. if read by movc instruction, the programmer will return 0ffh regardless of true data if movc is exe- cuted in a block with lower level lock. if read by the iap byte-verify command, then sfdt won?t update its data, i.e. sfdt will keep its old data unchanged, so the user?s application code will get ran- dom data based on the old sfdt value. this iap byte-verify command is executed in a block with lower level lock. the termination of the burst-program can be accom- plished by: 1) change to a new row address (note: the address range is different for the 4kx8 flash block 1 and for the 16/32k x 8 flash block 0.); 2) change to a new com- mand that requires a high to low transition of the ale/ prog# (for example, any erase or program command, 3) wait for time out limit to expire (20 s) before programming the next byte.
data sheet flashflex51 mcu sst89c54 / sst89c58 23 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 4.1.6 instructions to perform external host mode commands to program data into the memory array, apply power sup- ply voltage (v dd ) to v dd and rst pins, and perform the fol- lowing steps: 1. maintain rst high and toggle psen# from logic high to low, in sequence per the appropriate timing diagram. 2. raise ea# high (either v ih or v h ). 3. issue read-id command to enable the external host mode. 4. verify that the memory blocks or sectors for pro- gramming is in the erased state, ffh. if they are not erased, then erase them using the appropriate erase command. 5. select the memory location using the address lines (p1[7:0], p2[5:0], p3[5:4]). 6. present the data in on p0[7:0]. 7. pulse ale/prog#, observing minimum pulse width. 8. wait for low to high transition on ready/busy# (p3[3]). 9. repeat steps 5 - 8 until programming is finished. 10. verify the flash memory contents. 4.2 in-application programming mode the sst89c54/58 offers 20/36 kbyte of in-application pro- grammable flash memory. during in-application program- ming, the cpu of the microcontroller enters iap mode. the two blocks of flash memory allows the cpu to concurrently execute user code from one block, while the other is being reprogrammed. the cpu may also fetch code from an external memory while all internal flash is being repro- grammed. the mailbox registers (sfst, sfcm, sfal, sfah, sfdt and sfcf) located in the special function register (sfr), control and monitor the device?s erase and program process. table 4-3 outlines the commands and their associated set- tings of the mailbox registers. 4.2.1 in-application programming mode clock source during iap mode, both the cpu core and the flash control- ler unit (fcu) are driven off the external clock. however, an internal oscillator will provide timing references for program and erase operations. the duration of program and erase operations will be identical between external host mode and in-application mode. the internal oscillator is only turned on when required, and is turned off as soon as the flash operation is complete. 4.2.2 iap enable bit the iap enable bit, sfcf[6], initializes in-application pro- gramming mode. until this bit is set, all flash programming iap commands will be ignored.
24 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 4.2.3 in-application programming mode commands all of the following commands can only be initiated in the iap mode. in all situations, writing the control byte to the (sfcm) register will initiate all of the operations. all com- mands (except chip-erase) will not be enabled if the secu- rity features are enabled on the selected memory block. the two program commands are for programming new data into the memory array. the portion of the memory array to be programmed should be in the erased state, ffh. if the memory is not erased, then erase it with an appropriate erase command. do not write (program or erase) to a block that the code is currently fetching from. this will cause unpredictable program behavior and may corrupt program data. the chip-erase command erases all bytes in both memory blocks (16/32kb and 4kb). this command ignores the security lock status and will erase the security lock bits and re-map bits. the chip-erase command sequence is as follows: the block-erase command erases all bytes in one of the two memory blocks (16/32kb or 4kb). the selection of the memory block to be erased is determined by the (sfah[7]) of the superflash address register. the primary flash memory block 0 is selected (16/32kb) as follows: for sst89c58, sfah[7] = 0 selects block 0; for sst89c54, sfah[7:6] = 00 selects block 0. for both, sfah[7:4] = 1111b selects the secondary flash memory block 1 (4kb). the block-erase command sequence is as follows: the sector-erase command erases all of the bytes in a sector. the sector size for the primary flash memory block 0 is 128 bytes. the sector size for the secondary flash memory block 1 is 64 bytes. the selection of the sector to be erased is determined by the contents of sfah, sfal. please refer to figure 3-1 for an illustration of memory sector organization. the sector-erase com- mand sequence is as follows: set-up mov sfdt, #55h interrupt scheme mov sfcm, #81h polling scheme mov sfcm, #01h int1 interrupt indicates completion sfst[2] indicates operation completion iap enable orl sfcf, #40h 344 ill f39.4 set-up mov sfdt, #55h iap enable orl sfcf, #40h or interrupt scheme mov sfcm, #8dh polling scheme mov sfcm, #0dh erase 4 kblock mov sfah, #f0h erase 32 kblock mov sfah, #00h int1 interrupt indicates completion sfst[2] indicates operation completion 344 ill f40.8 load sector address mov sfah, #sector_addressh mov sfal, #sector_addressl interrupt scheme mov sfcm, #8bh polling scheme mov sfcm, #0bh int1 interrupt indicates completion sfst[2] indicates operation completion 344 ill f41.6 iap enable orl sfcf, #40h
data sheet flashflex51 mcu sst89c54 / sst89c58 25 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 the byte-program command programs data into a single byte location. the byte-program command sequence is as follows: the burst-program command programs data into half of a sector (row) which has the same row address, sequentially byte-by-byte. refer to the memory organization section in figure 3-1 for details. the movc instruction and all iap commands except burst-program are invalid during the burst-program cycle. the burst-program command sequence is as follows: move data to sfdt mov sfdt, #data interrupt scheme mov sfcm, #8eh polling scheme mov sfcm, #0eh int1 interrupt indicates completion sfst[2] indicates operation completion load byte address mov sfah, #byte_addressh mov sfal, #byte_addressl 344 ill f42.6 iap enable orl sfcf, #40h move data to sfdt mov sfdt, #data sfst[2] indicates burst-program completion interrupt scheme mov sfcm, #86h polling scheme mov sfcm, #06h int1 interrupt indicates completion sfst[3] indicates byte completion next same row address y n program another byte load byte address mov sfah, #byte_addressh mov sfal, #byte_addressl 344 ill f43.8 iap enable orl sfcf, #40h
26 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 the byte-verify command allows the user to verify that the sst89c54/58 has correctly performed an erase or pro- gram command. byte-verify command returns the data byte in sfdt. the user is required to check that the previ- ous flash operation has fully completed before issuing a byte-verify. byte-verify command execution time is short enough that there is no need to poll for command comple- tion and no interrupt is generated. the byte-verify com- mand sequence is as follows: prog-sb3, prog-sb2, prog-sb1 commands are used to program the security bits (see table 8-1). upon completion of any of those commands, the security options will be updated immediately. security bits previously in un-programmed state can be programmed by these commands. the prog-sb3, prog- sb2, prog-sb1 sequences are as follows: prog-rb1, prog-rb0 commands are used to program the re-map[1:0] bits (see table 3-1). these commands only change the re-map[1:0] bits and have no effect on map- en[1:0] until after a reset cycle. therefore, the effect of these commands is not immediate. re-map bits previously in un-programmed state can be programmed by these commands. the prog-rb1, prog- rb0 sequences are as follows: prog-sb3, prog-sb2, prog-sb1, prog-rb1, and prog-rb0 commands must reside only in block 0 (32 kbyte block) or external code memory. any such instructions issued from block 1 may cause unpredictable program behavior. 4.2.4 polling a command that uses the polling method to detect flash operation completion should poll on the flash_busy bit (sfst[2]). when flash_busy de-asserts (logic 0), the device is ready for the next operation. the busy bit (sfst[3]) is provided for burst-program. in between bytes within a burst sequence, the busy bit will become logic 0 to indicate that the next burst-program byte should be presented. completion of the full burst cycle is indicated also by flash_busy bit (sfst[2]). movc instruction may also be used for verification of the programming and erase operation of the flash memory. movc instruction will fail if it is directed at a flash block that is still busy. mov sfcm, #0ch sfdt register contains data load byte address mov sfah, #byte_addressh mov sfal, #byte_addressl 344 ill f44.5 iap enable orl sfcf, #40h set-up mov sfah, #80h mov sfdt, #55h or or int1# interrupt indicates completion polling sfst[2] indicates completion program sb2 mov sfcm, #03h or mov sfcm, #83h program sb1 mov sfcm, #0fh or mov sfcm, #8fh program sb3 mov sfcm, #05h or mov sfcm, #85h 344 ill f45.7 iap enable orl sfcf, #40h or set-up mov sfah, #80h mov sfdt, #55h or int1# interrupt indicates completion polling sfst[2] indicates completion program re-map [1] mov sfcm, #09h or mov sfcm, #89h program re-map [0] mov sfcm, #08h or mov sfcm, #88h 344 ill f46.6 iap enable orl sfcf, #40h
data sheet flashflex51 mcu sst89c54 / sst89c58 27 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 4.2.5 interrupt termination if interrupt termination is selected, (sfcm[7] is set), then an interrupt (int1) will be generated to indicate flash operation completion. under this condition, the int1 becomes an internal interrupt source. the int1# pin can now be used as a general purpose port pin and it cannot be a source of external interrupt 1. for an interrupt to occur, ex1 and ea bits of ie register must be set. the it1 bit of tcon register must also be set for edge trigger detection. important: the user cannot program security/re-map bits while code is running in block 1. the user can only pro- gram security sbx/re-map bits when code is running in external code memory or when code is running in block 0. the solution is to use mov sfah, #80h; before issuing any iap commands to program security bits or re-map bits. 5.0 timers/counters the sst89c54/58 have three 16-bit registers that can be used as either timers or event counters. the three tim- ers/counters are the timer 0 (t0), timer 1 (t1), and timer 2 (t2). each is designated with a pair of 8-bit registers in the sfrs. the pair consists of a most significant (high) byte and least significant (low) byte. the respective reg- isters are tl0, th0, tl1, th1, tl2, and th2. table 4-3: i n -a pplication p rogramming m ode c ommands operation sfah [7:0] sfal [7:0] sfdt [7:0] sfcm [6:0] 1 1. interrupt/polling enable for flash operation completion sfcm[7] = 1: interrupt enable for flash operation completion 0: polling enable for flash operation completion chip-erase x x 55h 01h block-erase ah 2 2. sfah[7] = 0 selects block 0 for sst89c58; sfah[7:6] = 00 selects block 0 for sst89c54; sfah[7:4] = fh selects block 1 note: x = don?t care; al = address low order byte; ah = addr ess high order byte; di = data input; do = data output all other values are in hex. sfcf[6] = 1 enables iap command. sfcf[6] = 0 disables iap command. x55h0dh sector-erase ah al x 0bh byte-program ah al di 0eh burst-program ah al di 06h byte-verify (read) ah al do 0ch prog-sb3 80h x 55h 05h prog-sb2 80h x 55h 03h prog-sb1 80h x 55h 0fh prog-rb1 80h x 55h 09h prog-rb0 80h x 55h 08h t4-3.4 344
28 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 6.0 serial i/o the sst89c54/58 serial i/o port is a full-duplex uart (universal asynchronous receiver/transmitter) that allows data to be transmitted and received simultaneously in hard- ware by the transmit and receive registers, respectively. the serial i/o port performs the function of an uart. the trans- mit and receive registers are both located in the serial data buffer (sbuf) special function register. writing to the sbuf register loads the transmit register, and reading from the sbuf register obtains the contents of the receive register. the serial i/o port has four modes of operation which are selected by the serial port mode specifier (sm0 and sm1) bits of the serial port control (scon) special function reg- ister. in all four modes, transmission is initiated by any instruction that uses the sbuf register as a destination register. reception is initiated in mode 0 when the receive interrupt (ri) flag bit of the serial port control (scon) spe- cial function register is cleared and the reception enable/ disable (ren) bit of the scon register is set. reception is initiated in other modes by the incoming start bit if the ren bit of the scon register is set. 7.0 watchdog timer the sst89c54/58 offer a hardware programmable watch- dog timer (wdt) for fail safe operation against software hangup and automatic reset recovery. to protect the system against software hangup, the soft- ware has to refresh the wdt within a user defined time period. if the software fails to do this periodic refresh, an internal hardware reset will be initiated if enabled (wdre=1). the software can be designed such that the wdt times out if the program does not work properly. it also times out if a software error is based on hardware related problems. the wdt in the sst89c54/58 share the same time base with the flash controller unit. when the flash controller unit is operating, the time base will be re-started by the hard- ware periodically, therefore delaying the time-out period of the watchdog timer. the upper 8-bits of the time base reg- ister are used as the reload register of the wdt. the internal oscillator that drives the wdt operates within a frequency range as shown in table 12-1. minimum clock cycle for the wdt is 7.7ms, typical 10ms. figure 7-1 provides a block diagram of the wdt. two sfrs (wdtc and wdtd) control watchdog timer operation. note: wdtd won?t be effective until bit wdt is set. a wdtd register can not be set to 0ffh. wdt timeout period = (255-wdtd) x 7.7ms (min.) figure 7-1: b lock d iagram of p rogrammable w atchdog t imer 344 ill f10.2 wdt upper byte wdt reset internal reset 7.7 ms min. counter clk ext. rst wdtc wdtd
data sheet flashflex51 mcu sst89c54 / sst89c58 29 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 8.0 security lock the security feature protects against software piracy and prevents the contents of the flash from being read by unau- thorized parties. it also protects against code corruption resulting from accidental erasing and programming to the internal flash memory locations. there are two different types of security locks in the sst89c54/58 security lock system, hard lock and softlock. (see figure 8-1 and table 8-1.) 8.1 hard lock when the hard lock is activated, the movc instructions executed from unlocked or softlocked program address space, are disabled from reading code bytes in hard locked memory blocks (see table 8-2). the hard lock can either lock both flash memory blocks or just lock the upper flash memory block (block 1). all external host and iap com- mands except for chip-erase are ignored by the hard locked memory blocks. 8.2 softlock softlock allows flash contents to be altered under a secure environment. this lock option allows the user to update program code in the softlocked memory block through in- application programming mode under a predetermined secure environment. for example, if the block 1 (4kb) memory is hard locked, and the block 0 (16kb/32kb) memory is softlocked, code residing in block 1 can pro- gram block 0. the following iap mode commands issued through the command mailbox register, sfcm, executed from a hard locked block can be operated on a softlocked block: block-erase, sector-erase, byte-program, burst- program and byte-verify. in external host mode, softlock behaves the same as a hard lock. 8.3 security lock status the three bits that indicate the sst89c54/58 security lock status, sb1, sb2 and sb3, are located in sfst[7:5]. as shown in figure 8-1 and table 8-1, the three security lock bits control the lock status of the primary and secondary blocks of memory. there are four distinct levels of security lock status. in the first level, none of the security lock bits are programmed and both blocks are unlocked. in the sec- ond level, although, both blocks are now locked and cannot be written, they are available for read operation via byte- verify. in the third level, three different options are available: block 1 hard lock / block 0 softlock, softlock on both blocks, and hard lock on both blocks. locking both blocks is the same as level 2 except read operation isn?t available. the fourth level of security is the most secure level. it doesn?t allow read/write of internal memory or boot from external memory. please note that for unused combina- tions of the security lock bit the chip will default to level 4 status. for details on how to program the security lock bits, refer to the external host programming mode (section 4.1) and in- application programming mode (section 4.2).
30 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 8-1: s ecurity l ock l evels table 8-1: s ecurity l ock o ptions level security lock bits 1,2 1. sfst[7:5] = security lock decoding bits (sb1, sb2, sb3) 2. p = programmed (cell logic state = 0); u = unprogrammed (cell logic state = 1) all unused combinations default to level 4, ?ppp? security status of: security type sfst[7:5] sb1 sb2 sb3 block 1 block 0 1 000 u u u unlock unlock no security features are enabled. 2 100 p u u hard lock hard lock movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea# is sampled and latched on reset, and further programming of the flash is dis- abled. 3110 101 p p p u u p hard lock hard lock level 2 plus verify disabled, both blocks locked. 010 u p u softlock softlock level 2 plus verify disabled, code in block 1 can pro- gram block 0 and vice versa. 001 u u p hard lock softlock level 2 plus verify disabled, code in block 1 can pro- gram block 0. 4 111 p p p hard lock hard lock same as level 3, hard lock/hard lock but mcu will start code execution from the internal memory regardless of ea#. t8-1.7 344 level 1 level 2 level 3 level 4 uuu/nn puu/ll ppu/ll pup/ll = upu/ss uup/ls ppp/ll 344 ill f38.1 note: p = programmed (cell logic state = 0), u = unprogrammed (cell logic state = 1) n = not locked, l = hard locked, s = softlocked
data sheet flashflex51 mcu sst89c54 / sst89c58 31 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 table 8-2: s ecurity l ock a ccess t able level sfst[7:5] source address 1 target address 2 byte-verify allowed movc allowed on c58/54 external host 3 iap 4 111b/011b 4 (hard lock on both blocks) block 0/1 block 0/1 n n y external n/a n/a y external block 0/1 n n n external n/a n/a y 3 101b/110b (hard lock on both blocks) block 0/1 block 0/1 n n y external n/a n/a y external block 0/1 n n n external n/a n/a y 001b (block 0 = softlock, block 1 = hard lock) block 0 block 0 n n y block 1 n n n 5 external n/a n y block 1 block 0 n y y block 1 n n y external n/a n/a y external block 0/1 n n n external n/a n/a y 010b (softlock on both blocks) block 0 block 0 n n y block 1 n y y external n/a n/a y block 1 block 0 n y y block 1 n n y external n/a n/a y external block 0/1 n n n external n/a n/a y 2 100b (hard lock on both blocks) block 0 block 0 y n y block 1 y n y external n/a n/a y block 1 block 0 y n y block 1 y n y external n/a n/a y external block 0/1 y n n external n/a n/a y 1 000b (unlock) block 0 block 0 y n y block 1 y y y external n/a n/a y block 1 block 0 y y y block 1 y n y external n/a n/a y external block 0/1 y y y external n/a n/a y t8-2.1 344 1. location of movc or iap instruction. 2. target address is the location of the instruction being read. 3. external host byte-verify access does not depend on a source address. 4. 011b is an unused combination and defaults to security level 4 5. movc is normally not allowed when accessing data in block 1 at addresses f000h-ffffh. movc is allowed when block 1 is re-mapped and target address is within 0000h-03ffh/07ffh/0fffh (1k/2k/4k re-map).
32 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 9.0 reset a system reset initializes the mcu and begins program execution at program memory location 0000h. the reset input for the sst89c54/58 is the rst pin. in order to reset the device, a logic level high must be applied to the rst pin for at least two machine cycles (24 clocks), after the oscilla- tor becomes stable. ale and psen# are weakly pulled high during reset. during reset, ale and psen# output a high level in order to perform correct reset. this level must not be affected by external element. a system reset will not affect the 256 bytes of on-chip ram while the sst89c54/ 58 is running, however, the contents of the on-chip ram during power up are indeterminate. all special function registers (sfr) return to their reset values, which are out- lined in tables 3-3 to 3-7. 9.1 power-on reset at initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algo- rithm has weakly pulled all pins high. powering up the device without a valid reset could cause the cpu to start executing instructions from an indeterminate location. such undefined states may inadvertently cor- rupt the code in the flash. when power is applied to the sst89c54/58, the rst pin must be high long enough for the oscillator to start up (usu- ally several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. an example of a method to extend the rst signal is to implement a rc circuit by connecting the rst pin to v dd through a 10f capacitor and to v ss through an 8.2 kohm resistor as shown in figure 10-1. note that if an rc circuit is being used, provisions should be made to ensure the v dd rise time does not exceed 10 ms. the oscillator start- up time depends on the crystal frequency. for a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. this method maintains the necessary relationship between v dd and rst to avoid programming at an indeterminate location, which may cause corruption in the flash memory. crystal typical start-up time 10mhz 1ms 1mhz 10ms
data sheet flashflex51 mcu sst89c54 / sst89c58 33 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 10.0 power-saving modes the sst89c54/58 provides power saving modes of opera- tion for applications where power consumption is critical. the two power saving modes are: power down and standby (stop clock). 10.1 power down mode the power down mode is entered by setting the pd bit in the pcon register. in power down mode, the clock is stopped and external interrupts are active for level sensitive interrupt only. the sst89c54/58 exits power down mode through either an enabled external level sensitive interrupt intx or a hard- ware reset. the interrupt clears the pd bit, the oscillator restarts and stablizes, then the program resumes execution beginning at the instruction immediately following the one which invoked the power down mode. the hardware reset redefines all the sfrs but does not change the on-chip ram. 10.2 standby mode (stop clock) standby mode is similar to power down mode, except that power down mode is initiated by a software command and standby mode is initiated by external hardware gating off the external clock to the sst89c54/58. the on-chip ram and sfr data are maintained in the standby mode. the device resumes operation at the next instruction when the clock is reapplied to the part. table 10-1 outlines the two power-saving modes, including entry and exit procedures and mcu functionality. figure 10-1: p ower -o n r eset c ircuit 344 ill f31.1 v dd v dd 10f + - 8.2k sst89c54/58 rst xtal2 xtal1 12mhz c 1 c 2
34 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 11.0 clock input options shown in figure 11-1 are the input and output of an inter- nal inverting amplifier (xtal1, xtal2), which can be con- figured for use as an on-chip oscillator. when driving the device from an external clock source, xtal2 should be left disconnected and xtal1 should be driven. at start-up, the external crystal oscillator may encounter a higher capacitive load at xtal1 due to interaction between the amplifier and its feedback capacitance. however, the capacitance will not exceed 15pf once the external signal meets the v il and v ih specifications. 11.1 recommended capacitor values for crystal oscillator crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one applica- tion to another. c1 and c2 capacitors should be adjusted appropriately for each design. table 11-1 below, shows the typical values for c1 and c2 by crystal type. table 10-1: sst89c54/58 p ower s aving m odes mode initiated by current drain state of mcu exited by power down mode software (set pd bit in pcon) mov pcon, #02h typically 15-20 a. min- imum v dd for power down mode is 2.7v. clk is stopped. on- chip sram and sfr data will be main- tained. ale and psen# signals at a low level during power down. external interrupts are only active for level sensi- tive interrupts, if enabled. enabled external level sensitive interrupt intx or hardware reset. start of interrupt clears pd bit and exits power down mode, after the isr reti instruction program resumes exe- cution beginning at the instruction following the one that invoked power down mode. a user could consider placing two or three nop instructions after the instruction that invokes power down mode to eliminate any problems, or by hardware reset. standby (stop clock) mode external hardware gates turn off the exter- nal clock input to the mcu. this gating should be synchro- nized with an input clock transition (low-to- high or high-to-low). typically 15-20 a. min- imum v dd for standby mode is 2.7v. clk is frozen. on-chip ram and sfr data is maintained. ale and psen# are maintained at the levels prior to the clock being frozen. gate on external clock. program execution resumes at the instruc- tion following the one during which the clock was gated off. t10-1.5 344 table 11-1: r ecommended values for c1 and c2 by crystal type crystal c1 = c2 quartz 20-30pf ceramic 40-50pf t11-1.1 344
data sheet flashflex51 mcu sst89c54 / sst89c58 35 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 11-1: o scillator c haracteristics 12.0 electrical specification absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to + 150c voltage on ea# pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14.0 v transient voltage (<20ns) on any other pin to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to +6.5v maximum i ol per i/o pins p1.5, p1.6, p1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma maximum i ol per i/o for all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ma package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5w through hole lead soldering temperature (10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300c surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. (based on package heat transfer limitations, not device power consumption.) note: this specification contains preliminary information on new products in production. the specifications are subj ect to change without notice. table 12-1: o perating r ange symbol description min. max unit t a ambient temperature under bias standard 0 +70 c industrial -40 +85 c v dd supply voltage 2.7 5.5 v f osc oscillator frequency for in-application programming 033mhz 0.25 33 mhz t12-1.0 344 344 ill f12.2 xtal2 xtal1 vss c 1 using the on-chip oscillator external clock drive c 2 xtal2 xtal1 vss external oscillator signal nc
36 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 table 12-2: r eliability c haracteristics symbol parameter minimum specification units test method n end 1 endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t12-2.1 344 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. table 12-3: ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 10 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 100 pf see figures 12-6 and 12-8 t12-3.0 344 table 12-4: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t12-4.0 344 table 12-5: p in i mpedance (v dd =3.3v, ta=25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance 2 2. pin capacitance is characterized but not tested. ea# pin is 25 pf max. v i/o = 0v 15 pf c in 1 input capacitance v in = 0v 12 pf l pin pin inductance 20 nh t12-5.1 344
data sheet flashflex51 mcu sst89c54 / sst89c58 37 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 12.1 dc electrical characteristics table 12-6: dc e lectrical c haracteristics t a = -40c to +85c, 33mh z devices ; v dd = 4.5-5.5v; v ss = 0v symbol parameter test conditions limits units min max v il input low voltage 4.5 < v dd < 5.5 -0.5 0.2 v dd - 0.1 v v ih input high voltage (ports 0,1,2,3) 4.5 < v dd < 5.5 0.2v dd + 0.9 v dd + 0.5 v v ih1 input high voltage (xtal1, rst) 4.5 < v dd < 5.5 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1.5, 1.6, 1.7) v dd = 4.5v i ol = 16 ma 1.0 v v ol output low voltage (ports 1, 2, 3) 1 v dd = 4.5v i ol = 100 a 2 0.3 v i ol = 1.6 ma 2 0.45 v i ol = 3.5 ma 2 1.0 v v ol1 output low voltage (port 0, ale, psen#) 1,3 v dd = 4.5v i ol = 200 a 2 0.3 v i ol = 3.2 ma 2 0.45 v v oh output high voltage (ports 1, 2, 3, ale, psen#) 4 v dd = 4.5v i oh = -10 a v dd - 0.3 v i oh = -30 a v dd - 0.7 v i oh = -60 a v dd - 1.5 v v oh1 output high voltage (port 0 in external bus mode) 4 v dd = 4.5v i oh = -200 a v dd - 0.3 v i oh = -3.2 ma v dd - 0.7 v i il logical 0 input current (ports 1, 2, 3) v in = 0.4v -1 -75 a i tl logical 1-to-0 transition current (ports 1, 2, 3) 5 v in = 2v -650 a i li input leakage current (port 0) 0.45 < v in < v dd -0.3 10 a r rst rst pulldown resistor 40 225 k ? i dd power supply current 6 in-application programming mode @ 12 mhz 70 ma @ 33 mhz 88 ma active mode @ 12 mhz 22 ma @ 33 mhz 45 ma standby (stop clock) mode t a = 0c to +70c 100 a t a = -40c to +85c 125 a power down mode minimum v dd = 2.7v t a = 0c to +70c 40 a t a = -40c to +85c 50 a t12-6.8 344
38 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 table 12-7: dc e lectrical c haracteristics t a = -40c to +85c, 12mh z devices ; v dd = 3.0-3.6v; v ss = 0v symbol parameter test conditions limits units min max v il input low voltage 2.7 < v dd < 3.3 -0.5 0.7 v v ih input high voltage (ports 0, 1, 2, 3) 2.7 < v dd < 3.3 0.2v dd + 0.9 v dd + 0.5 v v ih1 input high voltage (xtal1, rst) 2.7 < v dd < 3.3 0.7v dd v dd + 0.5 v v ol output low voltage (ports 1.5, 1.6, 1.7) v dd = 2.7v i ol = 16 ma 1.0 v v ol output low voltage (ports 1, 2, 3) 1 v dd = 2.7v i ol = 100 a 2 0.3 v i ol = 1.6 ma 2 0.45 v i ol = 3.5 ma 2 1.0 v v ol1 output low voltage (port 0, ale, psen#) 1,3 v dd = 2.7v i ol = 200 a 2 0.3 v i ol = 3.2 ma 2 0.45 v v oh output high voltage (ports 1, 2, 3, ale, psen#) 4 v dd = 2.7v i oh = -10 a v dd - 0.3 v i oh = -30 a v dd - 0.7 v i oh = -60 a v dd - 1.5 v v oh1 output high voltage (port 0 in external bus mode) 4 v dd = 2.7v i oh = -200 a v dd - 0.3 v i oh = -3.2 ma v dd - 0.7 v i il logical 0 input current (ports 1, 2, 3) v in = 0.4v -1 -75 a i tl logical 1-to-0 transition current (ports 1, 2, 3) 5 v in = 2v -650 a i li input leakage current (port 0) 0.45 < v in < v dd -0.3 10 a r rst rst pulldown resistor 40 225 k ? i dd power supply current 6 in-application programming mode 70 ma active mode 22 ma standby (stop clock) mode t a = 0c to +70c 70 a t a = -40c to +85c 88 a power down mode minimum v dd = 2.7v t a = 0c to +70c 40 a t a = -40c to +85c 50 a t12-7.6 344 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15ma maximum i ol per 8-bit port: 26ma maximum i ol total for all outputs: 71ma if i ol exceeds the test condition, v oh may exceed the related specification. pins ar e not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 & 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 & 3. the noise due to external bus capacitance discharging into the port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. i n the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 3. load capacitance for port 0, ale & psen# = 100pf, load capacitance for all other outputs = 80pf. 4. capacitive loading on ports 0 & 2 may cause the v oh , ale and psen# to momentarily fall below the v dd - 0.7 specification when the address bits are stabilizing.
data sheet flashflex51 mcu sst89c54 / sst89c58 39 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 12.2 ac electrical characteristics ac characteristics: (over operating conditions: load capacitance for port 0, ale#, and psen# = 100pf; load capacitance for all other outputs = 80pf) 5. pins for ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. 6. see figures 12-9, 12-10 and 12-11 and for test conditions. minimum v dd for power down is 2.7v. table 12-8: ac e lectrical c haracteristics (1 of 2) t a = -40c to +85c, v dd = 3.0-3.6v @12mh z ,4.5-5. 5v @ 33mh z , v ss = 0 symbol parameter oscillator units 12mhz 33mhz variable min max min max min max 1/t clcl oscillator frequency 033mhz t lhll ale pulse width 127 20 2t clcl - 40 ns t avll address valid to ale low 43 t clcl - 40 (3v) ns 5t clcl - 25 (5v) ns t llax address hold after ale low 53 t clcl - 30 (3v) ns 5t clcl - 25 (5v) ns t lliv ale low to valid instr in 234 4t clcl - 65 (3v) ns 55 4t clcl - 65 (5v) ns t llpl ale low to psen# low 53 t clcl - 30 (3v) ns 5t clcl - 25 (5v) ns t plph psen# pulse width 205 45 3t clcl - 45 ns t pliv psen# low to valid instr in 145 3t clcl - 55 (3v) ns 35 3t clcl - 55 (5v) ns t pxix input instr hold after psen# 00 0 ns t pxiz input instr float after psen# 59 t clcl - 25 (3v) ns 5t clcl - 25 (5v) ns t pxav psen# to address valid 75 22 t clcl - 8 ns t aviv address to valid instr in 312 5t clcl - 80 (3v) ns 70 5t clcl - 80 (5v) ns t plaz psen# low to address float 10 10 10 ns t rlrh rd# pulse width 400 80 6t clcl - 100 ns t wlwh write pulse width (we#) 400 80 6t clcl - 100 ns t rldv rd# low to valid data in 252 5t clcl - 90 (3v) ns 60 5t clcl - 90 (5v) ns t rhdx data hold after rd# 00 0 ns t rhdz data float after rd# 106 2t clcl - 60 (3v) ns 35 2t clcl - 25 (5v) ns t lldv ale low to valid data in 517 8t clcl - 90 (3v) ns 150 8t clcl - 90 (5v) ns t avdv address to valid data in 585 9t clcl - 90 (3v) ns 180 9t clcl - 90 (5v) ns t llwl ale low to rd# or wr# low 200 300 40 140 3t clcl - 50 3t clcl + 50 ns t avwl address to rd# or wr# low 203 4t clcl - 130 (3v) ns 45 4t clcl - 75 (5v) ns t qvwx data valid to wr# transition 33 t clcl - 50 (3v) ns 0t clcl - 30 (5v) ns
40 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 explanation of symbols each timing symbol has 5 characters. the first character is always a ?t? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. for example: t avll = time from address valid to ale low t llpl = time from ale low to psen# low t whqx data hold after wr# 33 t clcl - 50 (3v) ns 3t clcl - 27 (5v) ns t qvwh data valid to wr# high 433 7t clcl - 150 (3v) ns 140 7t clcl - 70 (5v) ns t rlaz rd# low to address float 00 0 ns t whlh rd# to wr# high to ale high 43 123 t clcl - 40 (3v) t clcl + 25 (3v) ns 555 t clcl - 25 (5v) t clcl + 25 (5v) ns t12-8.3 344 a: address q: output data c: clock r: rd# signal d: input data t: time h: logic level high v: valid i: instruction (program memory contents) w: wr# signal l: logic level low or ale x: no longer a valid logic level p: psen# z: high impedance (float) table 12-8: ac e lectrical c haracteristics (c ontinued ) (2 of 2) t a = -40c to +85c, v dd = 3.0-3.6v @12mh z ,4.5-5. 5v @ 33mh z , v ss = 0 symbol parameter oscillator units 12mhz 33mhz variable min max min max min max
data sheet flashflex51 mcu sst89c54 / sst89c58 41 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 12-1: e xternal p rogram m emory r ead c ycle figure 12-2: e xternal d ata m emory r ead c ycle 344 ill f13.5 port 2 port 0 psen# ale a0 - a7 t llax t plaz t pxiz t llpl t aviv t avll t pxix t lhll t lliv t pliv t plph instr in a8 - a15 a8 - a15 a0 - a7 t pxav 344 ill f14.4 port 2 port 0 rd# psen# ale t lhll p2[0:7] or a8-a15 from dph a0-a7 from ri or dpl t avdv t avwl data i n instr in t rlaz t avll t llax t llwl t lldv t rlrh t rldv t rhdz t whlh t rhdx a8-a15 from pch a0-a7 from pcl
42 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 12-3: e xternal d ata m emory w rite c ycle figure 12-4: e xternal c lock d rive w aveform table 12-9: e xternal c lock d rive symbol parameter oscillator units 12mhz 33mhz variable minmaxminmax min max 1/t clcl oscillator frequency 0 33 mhz t clcl clock period 83 30 ns t chcx high time 10.5 0.35t clcl 0.65t clcl ns t clcx low time 10.5 0.35t clcl 0.65t clcl ns t clch rise time 20 5 ns t chcl fall time 20 5 ns t12-9.3 344 344 ill f15.4 port 2 port 0 wr# psen# ale t lhll p2[0:7] or a8-a15 from dph a0-a7 from ri or dpl data out instr in t avll t avwl t llwl t llax t qvwx t wlwh t qvwh t whqx t whlh a8-a15 from pch a0-a7 from pcl 0.2 v dd -0.1 0.45 v t chcl t clcl t clch t clcx t chcx 0.7 v dd v dd -0.5 344 ill f30.1
data sheet flashflex51 mcu sst89c54 / sst89c58 43 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 12-5: s hift r egister m ode t iming w aveforms figure 12-6: ac i nput /o utput t est w aveforms figure 12-7: f loat w aveform table 12-10: s erial p ort t iming symbol parameter oscillator units 12mhz 33mhz variable min max min max min max t xlxl serial port clock cycle time 1 0.36 12t clcl s t qvxh output data setup to clock rising edge 700 167 10t clcl - 133 ns t xhqx output data hold after clock rising edge 50 2t clcl - 117 ns 10 2t clcl - 50 ns t xhdx input data hold after clock rising edge 0 0 0 ns t xhdv clock rising edge to input data valid 700 167 10t clcl - 133 ns t12-10.2 344 344 ill f29.0 ale 0 instruction clock output data write to sbuf valid valid valid valid valid valid valid valid input data clear ri 01 2 34 567 t xlxl t qvxh t xhqx t xhdv t xhdx set ti set r i 1 2 3 4 5 6 7 8 v lt ac inputs during testing are driven at v iht (v dd -0.5v) for logic "1" and v ilt (0.45v) for a logic "0". measurement reference points for inputs and outputs are at v ht (0.2v dd + 0.9) and v lt (0.2v dd - 0.1) v ht v iht v ilt 344 ill f28a.2 note: v ht - v high test v lt - v low test v iht -v input high test v ilt - v input low test for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh = 20ma. v load +0.1v v load -0.1v v ol -0.1v timing reference points v ol +0.1v v load 344 ill f28b.3
44 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 12-8: a t est l oad e xample figure 12-9: i dd t est c ondition , a ctive m ode figure 12-10: i dd t est c ondition , p ower d own m ode figure 12-11: i dd t est c ondition , s tandby (s top c lock ) m ode note: idle mode is not supported. 344 ill f48.0 to tester to dut c l v dd v dd v dd v dd p0 ea# rst xtal2 (nc) clock signal all other pins disconnected 8xc5x xtal1 344 ill f26.0 v ss i dd v dd v dd v dd v dd = 3 or 5v p0 ea# rst xtal2 (nc) all other pins disconnected 8xc5x xtal1 344 ill f25.2 v ss i dd v dd v dd v dd v dd = 5v p0 ea# rst xtal2 (nc) all other pins disconnected 8xc5x xtal1 344 ill f33.3 v ss i dd
data sheet flashflex51 mcu sst89c54 / sst89c58 45 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 table 12-11: f lash m emory p rogramming /v erification p arameters parameter 1,2 symbol min max units reset setup time t su 3s read-id command width t rd 1s psen# setup time t es 1.125 s address, command, data setup time t ads 0ns chip-erase time t ce 11.7 ms block-erase time t be 9.4 ms sector-erase time t se 1.1 2.3 ms program setup time t prog 1.2 s address, command, data hold t dh 0ns byte-program time 3 t pb 110 s verify command delay time t oa 50 ns verify high order address delay time t aha 50 ns verify low order address delay time t ala 50 ns first burst-program byte time 4 t bup1 85 s burst-program time 3,4 t bup 31 45 s burst-program recovery 4 t buprcv 110 s burst-program time-out limit t bupto 20 s t12-11.4 344 1. program and erase times will scale inversely relative to programming clock frequency. 2. all timing measurements are from the 50% of the input to 50% of the output. 3. each byte must be erased before program. 4. external host mode only.
46 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 12.3 flash memory programming timing diagrams with external host mode figure 12-12: r ead -id read chip signature and identification registers at the addressed location. figure 12-13: c hip -e rase erase both flash memory blocks. security lock is ignored and the security bits are erased too. 344 ill f02.6 0030h t su t es rst psen# ale/prog# ea# p3[5:4] ,p2[5:0] ,p1 p2[7:6] ,p3[7:6] p0 0000b t rd bfh 0031h 0000b t rd e4h/e2h rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] 0001b t ce t prog t ads 344 ill f03.4 t es t su t dh ea#
data sheet flashflex51 mcu sst89c54 / sst89c58 47 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 12-14: b lock -e rase erase one of the flash memory blocks, if the security lock is not activated on that flash memory block. the highest address bits a[15:12] determines which block is erased. for example, if a15 is ?0?, primary flash memory block is erased. if a[15:12] = ?1111b?, the secondary block is erased. figure 12-15: s ector -e rase erase the addressed sector if the security lock is not activated on that flash memory block. rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] p3[5:4], p2[5:0] 1101b ah t be t prog t su t ads 344 ill f04.5 t es t dh ea# rst psen# ale/prog# p3[3] p3[7:6], p2[7:6] p3[5:4], p2[5:0] 1011b ah t se t prog t ads 344 ill f05.4 p1 al t dh t su t es ea#
48 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 12-16: b yte -p rogram ; p rog -sb3, p rog -sb2, p rog -sb1, p rog -rb1, and p rog -rb0 program the addressed code byte if the byte location has been successfully erased and not yet programmed. byte-program operation is only allowed when the security lock is not activated on that flash memory block. rst psen# ale/prog# ea# p3[3] p3[5:4], p2[5:0] p1 ah al t pb t prog t ads 344 ill f06.8 p0 p3[7:6], p2[7:6] di 1110b* * see table 4-1 for control signal assignments for prog-sbx and prog-rbx. t dh t su t es
data sheet flashflex51 mcu sst89c54 / sst89c58 49 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 figure 12-17: b urst -p rogram program the entire addressed row by burst programming each byte sequentially within the row if the byte loca- tion has been successfully erased and not yet programmed. this operation is only allowed when the security lock is not activated on that flash memory block. figure 12-18: b yte -v erify read the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. rst psen# ale/prog# p3[3] row address byte address row address byte address t prog t ads 344 ill f07.4 p0 p3[7:6], p2[7:6] di byte address di row address byte address di 0110b t bup1 t dh t dh t dh t bup t bup t buprcv 16k/32k block row address = a15: a6; byte address = a5:a0 4k block row address = a15: a5; byte address = a4:a0 t su t es ea# 344 ill f08.3 p3[5:4], p2[5:0] al do 1100b p3[7:6], p2[7:6] t su rst psen# ale/prog# ea# p0 p1 t ala t oa t aha ah t es
50 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 13.0 product ordering information 13.1 valid combinations valid combinations for sst89c54 sst89c54-33-c-pi sst89c54-33-c-nj sst89c54-33-c-tqj sst89c54-33-i-pi sst89c54-33-i-nj sst89c54-33-i-tqj valid combinations for sst89c58 sst89c58-33-c-pi sst89c58-33-c-nj sst89c58-33-c-tqj sst89c58-33-i-pi sst89c58-33-i-nj sst89c58-33-i-tqj note: valid combinations are those products in mass production or wil l be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. device speed suffix1 suffix2 sst89 c 5x -33 -x x -x x package modifier i = 40 pins j = 44 leads package type p = pdip n = plcc tq = tqfp operation temperature c = commercial = 0c to +70c i = industrial = -40c to +85c release id blank = initial release a = first enhancement operating frequency 33 = 0-33mhz feature set and flash memory size 54 = c52 feature set + 16(20) kbyte 58 = c52 feature set + 32(36) kbyte note: 4k additional flash can be enabled via vis bit in sfcf voltage range c = 2.7-5.5v device family 89 = c51 core
data sheet flashflex51 mcu sst89c54 / sst89c58 51 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 14.0 packaging diagrams 40- pin p lastic d ual i n -l ine p ins (pdip) sst p ackage c ode : pi 44- lead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nj 40.pdippi-ill.7 pin #1 identifier c l 40 1 base plane seating plane .220 max. 12? 4 places .600 bsc .100 bsc .100 ? .200 .015 .022 .045 .055 .063 .090 .015 min. .065 .075 2.020 2.070 .008 .012 0? 15? .600 .625 .530 .557 note: 1. complies with jedec publication 95 ms-011 ac dimensions (except as noted), although some dimensions may be more string ent. ? = jedec min is .115; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .025 .045 .013 .021 .590 .630 .100 .112 .020 min. .165 .180 top view side view bottom view 144 .026 .032 .500 ref. 44.plcc.nj-ill.7 note: 1. complies with jedec publication 95 ms-018 ac dimensions (except as noted), although some dimensions may be more string ent. ? = jedec min is .650; sst min is less stringent 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc. .050 bsc. .026 .032 .042 .056 .646 ? .656 .042 .048 .042 .048 optional pin #1 identifier .646 ? .656 .685 .695 .685 .695 .020 r. max. .147 .158 r. x45?
52 data sheet flashflex51 mcu sst89c54 / sst89c58 ?2002 silicon storage technology, inc. s71131-03-000 9/02 344 44- lead t hin q uad f lat p ack (tqfp) sst p ackage c ode : tqj .45 .75 10.00 bsc 12.00 bsc 10.00 bsc 12.00 bsc 1.00 ref 0?- 7? 1 11 33 23 12 22 44 34 1.2 max. .95 1.05 .05 .15 pin #1 identifier .30 .45 .09 .20 .80 bsc note: 1. complies with jedec publication 95 ms-026 acb dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (0.05) mm. 4. package body dimensions do not include mold flash. maximum allowable mold flash is .25mm. 44.tqfp-tqj-ill.6 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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